AT24C02B-PU

Product Summary

Description
The AT24C02B provides 2048 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The AT24C02B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead
TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface.
In addition, the AT24C02B is available in 1.8V (1.8V to 5.5V) version.

 

Parametrics

ble 3.  Pin Capacitance
(1)
Applicable over recommended operating range from TA
 = 25°C, f = 1.0 MHz, VCC
 = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0
, A1
, A2
, SCL) 6 pF VIN = 0V
Table 4.  DC Characteristics
Applicable over recommended operating range from: TAI
 = –40°C to +85°C, VCC
 = +1.8V to +5.5V, VCC
= +1.8V to +5.5V
(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1
Supply Voltage 1.8 5.5 V
VCC2
Supply Voltage 2.5 5.5 V
VCC3
Supply Voltage 2.7 5.5 V
VCC4
Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
ICC
Supply Current VCC
 = 5.0V WRITE at 100 kHz 2.0 3.0 mA
ISB1
Standby Current VCC = 1.8V VIN = VCC or VSS
0.6 3.0 μA
ISB2
Standby Current VCC = 2.5V VIN = VCC or VSS
1.4 4.0 μA
ISB3
Standby Current VCC
 = 2.7V VIN
 = VCC
 or VSS
1.6 4.0 μA
ISB4
Standby Current VCC = 5.0V VIN = VCC or VSS
8.0 18.0 μA
ILI
Input Leakage Current VIN
 = VCC
 or VSS
0.10 3.0 μA
ILO Output Leakage Curre

 

Features

Features
? Low-voltage and Standard-voltage Operation
– 1.8 (VCC
 = 1.8V to 5.5V)
? Internally Organized 256 x 8 (2K)
? Two-wire Serial Interface
? Schmitt Trigger, Filtered Inputs for Noise Suppression
? Bidirectional Data Transfer Protocol
? 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
? Write Protect Pin for Hardware Data Protection
? 8-byte Page (2K) Write Modes
? Partial Page Writes Allowed
? Self-timed Write Cycle (5 ms max)
? High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
? 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
? Lead-free/Halogen-free
? Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Diagrams

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02B features a low-power standby mode which is
enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.