(China (Mainland))
Product Summary
The CY62167DV30LL-55BVXI is a high-performance CMOS static RAM organized as 1M words by 16 bits. The CY62167DV30LL-55BVXI features advanced circuit design to provide ultra-low active current. The CY62167DV30LL-55BVXI is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The CY62167DV30LL-55BVXI also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The CY62167DV30LL-55BVXI can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH),or during a Write operation (CE1 LOW, CE2 HIGH and WE LOW).
Parametrics
CY62167DV30LL-55BVXI absolute maximum ratings : (1)Storage Temperature: –65°C to +150°C; (2)Ambient Temperature with Power Applied: –55°C to +125°C; (3)Supply Voltage to Ground Potential: –0.2V to VCC + 0.3V; (4)DC Voltage Applied to Outputs in High-Z State: –0.2V to VCC + 0.3V; (5)DC Input Voltage: –0.2V to VCC + 0.3V.
Features
CY62167DV30LL-55BVXI features: (1)TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM; (2)Very high speed: 45 ns; (3)Wide voltage range: 2.2V 3.6V; (4)Ultra-low active power: Typical active current: 2 mA @ f = 1 MHz; typical active current: 18.5 mA @ f = fMax (45 ns speed); (5)Ultra-low standby power; (6)Easy memory expansion with CE1, CE2 and OE features; (7)Automatic power-down when deselected; (8)CMOS for optimum speed/power; (9)Available in Pb-free and non Pb-free 48-ball VFBGA and 48-pin TSOP I package.
Diagrams
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 CY62167DV30LL-55BVXI |
Cypress Semiconductor |
SRAM SLO 3.0V SUPER LO PWR 1MEGX16 SRAM IND |
Data Sheet |
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CY62167DV30LL-55BVXIT |
Cypress Semiconductor |
SRAM SLO 1.8V SUPER LO PWR 1MEGX16 SRAM IND |
Data Sheet |
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